/* SPDX-License-Identifier: GPL-2.0 */
/**
 * gmac_csp.h - CSP definitions of LomboTech GMAC Driver.
 *
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __GMAC_CSP_H__
#define __GMAC_CSP_H__

#include <linux/bitops.h>

enum lgmac_tx_status {
	LGMAC_TX_OK		= 0,
	LGMAC_TX_DMA_OWN	= BIT(0),
	LGMAC_TX_NOT_LS		= BIT(1),
	LGMAC_TX_ERROR		= BIT(2),
};

enum lgmac_rx_status {
	LGMAC_RX_OK		= 0,
	LGMAC_RX_DMA_OWN	= BIT(0),
	LGMAC_RT_NOT_LS		= BIT(1),
	LGMAC_RX_DISCARD	= BIT(2),
};

struct dma_desc {
	__le32 des0;
	__le32 des1;
	__le32 des2;
	__le32 des3;
};

/**
 * csp_gmac_desc_set_addr - set buffer address of dma desc.
 * @desc: pointer to dma desc struct.
 * @addr: buffer address.
 */
void csp_gmac_desc_set_addr(struct dma_desc *desc, u32 addr);

/**
 * csp_gmac_desc_get_addr - get buffer address of dma desc.
 * @desc: pointer to dma desc struct.
 *
 * return buffer address.
 */
u32 csp_gmac_desc_get_addr(struct dma_desc *desc);

/**
 * csp_gmac_desc_tx_set_owner - set DMA as the owner of tx desc.
 * @desc: pointer to dma desc struct.
 */
void csp_gmac_desc_tx_set_owner(struct dma_desc *desc);

/**
 * csp_gmac_desc_tx_set_ic -  set "Interrupt on Completion" bit of tx desc.
 * @desc: pointer to dma desc struct.
 */
void csp_gmac_desc_tx_set_ic(struct dma_desc *desc);

/**
 * csp_gmac_desc_tx_set_mss -  set MSS by tx context desc.
 * @desc: pointer to dma desc struct.
 * @mss: maximum segment size.
 */
void csp_gmac_desc_tx_set_mss(struct dma_desc *desc, u32 mss);

/**
 * csp_gmac_desc_tx_init - init tx desc.
 * @desc: pointer to dma desc struct.
 */
void csp_gmac_desc_tx_init(struct dma_desc *desc);

/**
 * csp_gmac_desc_tx_release - clear tx desc after transmit.
 * @desc: pointer to dma desc struct.
 */
void csp_gmac_desc_tx_release(struct dma_desc *desc);

/**
 * csp_gmac_desc_tx_prepare - prepare tx desc before transmit.
 * @desc: pointer to dma desc struct.
 * @len: buffer length.
 * @pktlen: packet length.
 * @tx_own: to set DMA as the owner of the desc or not.
 * @fs: is the first segment or not.
 * @ls: is the last segment or not.
 * @csum: checksum insert or not.
 */
void csp_gmac_desc_tx_prepare(struct dma_desc *desc, int len, u32 pktlen,
			      bool tx_own, bool fs, bool ls, bool csum);

/**
 * csp_gmac_desc_tx_tso_prepare - prepare tx tso desc before transmit.
 * @desc: pointer to dma desc struct.
 * @len1: buffer1 length.
 * @len2: buffer2 length.
 * @tx_own: to set DMA as the owner of the desc or not.
 * @fs: is the first segment or not.
 * @ls: is the last segment or not.
 * @tcphdrlen: tcp header length.
 * @tcppayloadlen: tcp payload length.
 */
void csp_gmac_desc_tx_tso_prepare(struct dma_desc *desc, u32 len1, u32 len2,
				  bool tx_own, bool fs, bool ls,
				  u32 tcphdrlen, u32 tcppayloadlen);

/**
 * csp_gmac_desc_tx_status - get tx status from tx desc after transmit.
 * @desc: pointer to dma desc struct.
 * @status: pointer to net device status struct.
 *
 * return tx status.
 */
int csp_gmac_desc_tx_status(struct dma_desc *desc,
			    struct net_device_stats *status);

/**
 * csp_gmac_desc_rx_set_owner - set DMA as the owner of rx desc.
 * @desc: pointer to dma desc struct.
 * @disable_ic: disable "Interrupt on Completion" function or not.
 */
void csp_gmac_desc_rx_set_owner(struct dma_desc *desc, u32 disable_ic);

/**
 * csp_gmac_desc_rx_init - init rx desc.
 * @desc: pointer to dma desc struct.
 * @disable_ic: disable "Interrupt on Completion" function or not.
 */
void csp_gmac_desc_rx_init(struct dma_desc *desc, u32 disable_ic);

/**
 * csp_gmac_desc_rx_frame_len - get frame length from rx desc after receive.
 * @desc: pointer to dma desc struct.
 *
 * return frame length.
 */
u32 csp_gmac_desc_rx_frame_len(struct dma_desc *desc);

/**
 * csp_gmac_desc_rx_status - get rx status from rx desc after receive.
 * @desc: pointer to dma desc struct.
 * @status: pointer to net device status struct.
 *
 * return rx status.
 */
int csp_gmac_desc_rx_status(struct dma_desc *desc,
			    struct net_device_stats *status);

/**
 * csp_gmac_set_gmii_tx_clk_invert - enable or disable mii/gmii tx clock invert.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_gmii_tx_clk_invert(void *base_addr, u32 enable);

/**
 * csp_gmac_set_rmii_tx_clk_invert - enable or disable rmii tx clock invert.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_rmii_tx_clk_invert(void *base_addr, u32 enable);

/**
 * csp_gmac_set_rmii_tx_clk_src - set rmii tx clock source.
 * @base_addr: base address of gmac controller.
 * @src: 0, use internal-OSC; !0, use external-OSC.
 */
void csp_gmac_set_rmii_tx_clk_src(void *base_addr, u32 src);

/**
 * csp_gmac_set_phy_interface - set phy interface type.
 * @base_addr: base address of gmac controller.
 * @phy_if: phy interface type.
 */
void csp_gmac_set_phy_interface(void *base_addr, u32 phy_if);

/**
 * csp_gmac_enable_clk_gate - enable clock gate.
 * @base_addr: base address of gmac controller.
 * @mask: clock gate bits to be enabled.
 */
void csp_gmac_enable_clk_gate(void *base_addr, u32 mask);

/**
 * csp_gmac_disable_clk_gate - disable clock gate.
 * @base_addr: base address of gmac controller.
 * @mask: clock gate bits to be disabled.
 */
void csp_gmac_disable_clk_gate(void *base_addr, u32 mask);

/**
 * csp_gmac_set_rx_smp_delay - set rx sample clock delay.
 * @base_addr: base address of gmac controller.
 * @delay: delay value.
 */
void csp_gmac_set_rx_smp_delay(void *base_addr, u32 delay);

/**
 * csp_gmac_set_tx_drv_delay - set tx driver clock delay.
 * @base_addr: base address of gmac controller.
 * @delay: delay value.
 */
void csp_gmac_set_tx_drv_delay(void *base_addr, u32 delay);

/**
 * csp_gmac_set_base_config - set base configuration.
 * @base_addr: base address of gmac controller.
 * @mask: base configuration bits to be set.
 */
void csp_gmac_set_base_config(void *base_addr, u32 mask);

/**
 * csp_gmac_clr_base_config - clear base configuration.
 * @base_addr: base address of gmac controller.
 * @mask: base configuration bits to be cleared.
 */
void csp_gmac_clr_base_config(void *base_addr, u32 mask);

/**
 * csp_gmac_set_checksum_offload - enable or disabled rx checksum offload.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_checksum_offload(void *base_addr, u32 enable);

/**
 * csp_gmac_set_duplex_mode - set duplex mode.
 * @base_addr: base address of gmac controller.
 * @mode: 0, half-duplex mode; !0, full-duplex mode.
 */
void csp_gmac_set_duplex_mode(void *base_addr, u32 mode);

/**
 * csp_gmac_set_speed - set speed in MII/RMII/RGMII interface.
 * @base_addr: base address of gmac controller.
 * @speed: speed, should be 10/100/1000.
 */
void csp_gmac_set_speed(void *base_addr, u32 speed);

/**
 * csp_gmac_set_transmitter - enable or disable the Transmitter.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_transmitter(void *base_addr, u32 enable);

/**
 * csp_gmac_set_receiver - enable or disable the Receiver.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_receiver(void *base_addr, u32 enable);

/**
 * csp_gmac_set_frame_filter - set frame filter configuration.
 * @base_addr: base address of gmac controller.
 * @flr: frame filter configuration.
 */
void csp_gmac_set_frame_filter(void *base_addr, u32 flr);

/**
 * csp_gmac_set_filter_hash_lo - set low 32 bits of address filter hash table.
 * @base_addr: base address of gmac controller.
 * @lo: low 32 bits of the hash table.
 */
void csp_gmac_set_filter_hash_lo(void *base_addr, u32 lo);

/**
 * csp_gmac_set_filter_hash_hi - set upper 32 bits of address filter hash table.
 * @base_addr: base address of gmac controller.
 * @hi: upper 32 bits of the hash table.
 */
void csp_gmac_set_filter_hash_hi(void *base_addr, u32 hi);

/**
 * csp_gmac_set_tx_flow_control - set tx flow control.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @enable: 0, disable; !0, enable.
 * @duplex: 0, half-duplex mode; !0 full-duplex mode.
 * @time: pause time.
 */
void csp_gmac_set_tx_flow_control(void *base_addr, u32 queue, u32 enable,
				  u32 duplex, u32 time);

/**
 * csp_gmac_set_rx_flow_control - set rx flow control.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_rx_flow_control(void *base_addr, u32 enable);

/**
 * csp_gmac_set_tx_queue_priority - set tx queue priority.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @prio: priority.
 */
void csp_gmac_set_tx_queue_priority(void *base_addr, u32 queue, u32 prio);

/**
 * csp_gmac_set_rx_flow_control - set rx queue enable.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @mode: AV or DCB mode, or neither.
 */
void csp_gmac_set_rx_queue_enable(void *base_addr, u32 queue, u32 mode);

/**
 * csp_gmac_set_rx_queue_routing - set rx queue routing.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @mode: AV or DCB mode.
 */
void csp_gmac_set_rx_queue_routing(void *base_addr, u32 queue, u32 mode);

/**
 * csp_gmac_set_rx_queue_priority - set rx queue priority.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @prio: priority.
 */
void csp_gmac_set_rx_queue_priority(void *base_addr, u32 queue, u32 prio);

/**
 * csp_gmac_get_core_int_status - get core interrupt status.
 * @base_addr: base address of gmac controller.
 *
 * return core interrupt status.
 */
u32 csp_gmac_get_core_int_status(void *base_addr);

/**
 * csp_gmac_set_core_int_enable - set core interrupt enable bits.
 * @base_addr: base address of gmac controller.
 * @mask: interrupt enable bits to be set.
 */
void csp_gmac_set_core_int_enable(void *base_addr, u32 mask);

/**
 * csp_gmac_get_int_enable - get core interrupt enable bits.
 * @base_addr: base address of gmac controller.
 *
 * return interrupt enable bits.
 */
u32 csp_gmac_get_core_int_enable(void *base_addr);

/**
 * csp_gmac_set_lpi_mode - enable or disable lpi mode.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_lpi_mode(void *base_addr, u32 enable);

/**
 * csp_gmac_get_lpi_ctrl_status - get lpi control and interrupt status.
 * @base_addr: base address of gmac controller.
 *
 * Some bits of this register will be cleared by a read into this register.
 *
 * return lpi control and interrupt status.
 */
u32 csp_gmac_get_lpi_ctrl_status(void *base_addr);

/**
 * csp_gmac_clear_lpi_ctrl_status - clear lpi control and interrupt status.
 * @base_addr: base address of gmac controller.
 * @mask: interrupt bits to be clear.
 */
void csp_gmac_clear_lpi_ctrl_status(void *base_addr, u32 mask);

/**
 * csp_gmac_set_lpi_pls - set lpi phy link status.
 * @base_addr: base address of gmac controller.
 * @link: 0, link down; !0, link up(okay).
 */
void csp_gmac_set_lpi_pls(void *base_addr, u32 link);

/**
 * csp_gmac_set_lpi_timer - set lpi timer parameter.
 * @base_addr: base address of gmac controller.
 * @lst: link status timer, unit: ms.
 * @twt: transmit waitting timer, unit: us.
 */
void csp_gmac_set_lpi_timer(void *base_addr, u32 lst, u32 twt);

/**
 * csp_gmac_fix_mdio_clock - fix mdio clock.
 * @base_addr: base address of gmac controller.
 * @clk_rate: core clock rate of gmac controller.
 */
void csp_gmac_fix_mdio_clock(void *base_addr, u32 clk_rate);

/**
 * csp_gmac_check_mdio_busy - check if mdio is busy.
 * @base_addr: base address of gmac controller.
 *
 * return 0 if mdio is not busy; 1 if busy.
 */
u32 csp_gmac_check_mdio_busy(void *base_addr);

/**
 * csp_gmac_config_mdio_read - config and click mdio read.
 * @base_addr: base address of gmac controller.
 * @phy_addr: phy device address.
 * @phy_reg: phy register address.
 */
void csp_gmac_config_mdio_read(void *base_addr, u32 phy_addr, u32 phy_reg);

/**
 * csp_gmac_config_mdio_write - config and click mdio write.
 * @base_addr: base address of gmac controller.
 * @phy_addr: phy device address.
 * @phy_reg: phy register address.
 */
void csp_gmac_config_mdio_write(void *base_addr, u32 phy_addr, u32 phy_reg);

/**
 * csp_gmac_mdio_reset - mdio reset.
 * @base_addr: base address of gmac controller.
 */
void csp_gmac_mdio_reset(void *base_addr);

/**
 * csp_gmac_mdio_read_data - mdio read data.
 * @base_addr: base address of gmac controller.
 *
 * return the data.
 */
u32 csp_gmac_mdio_read_data(void *base_addr);

/**
 * csp_gmac_mdio_write_data - mdio write data.
 * @base_addr: base address of gmac controller.
 * @data: data to be write.
 */
void csp_gmac_mdio_write_data(void *base_addr, u32 data);

/**
 * csp_gmac_set_clear_on_write - enable or disabled register clear on write.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_clear_on_write(void *base_addr, u32 enable);

/**
 * csp_gmac_set_mac_addr - set mac address.
 * @base_addr: base address of gmac controller.
 * @addr: buffer of mac address.
 */
void csp_gmac_set_mac_addr(void *base_addr, u8 *addr);

/**
 * csp_gmac_get_mac_addr - get mac address.
 * @base_addr: base address of gmac controller.
 * @addr: buffer to receive the mac address.
 */
void csp_gmac_get_mac_addr(void *base_addr, u8 *addr);

/**
 * csp_gmac_set_tx_algorithm - set tx scheduling algorithm.
 * @base_addr: base address of gmac controller.
 * @algro: tx scheduling algorithm.
 */
void csp_gmac_set_tx_algorithm(void *base_addr, u32 algro);

/**
 * csp_gmac_set_rx_algorithm - set rx arbitration algorithm.
 * @base_addr: base address of gmac controller.
 * @algro: receive arbitration algorithm.
 */
void csp_gmac_set_rx_algorithm(void *base_addr, u32 algro);

/**
 * csp_gmac_get_mtl_int_status - get mtl interrupt status.
 * @base_addr: base address of gmac controller.
 *
 * return mtl interrupt status.
 */
u32 csp_gmac_get_mtl_int_status(void *base_addr);

/**
 * csp_gmac_set_rx_queue_map - map rx queue to dma channel.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @ch: dma channel number.
 */
void csp_gmac_set_rx_queue_map(void *base_addr, u32 queue, u32 ch);

/**
 * csp_gmac_set_tx_queue_threshold - set tx Store-and-Forward or set threshold.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @sf: 0, disable tx Store-and-Forward; !0, enable.
 * @th: tx threshold to set, if tx Store-and-Forward is disabled.
 */
void csp_gmac_set_tx_queue_threshold(void *base_addr, u32 queue,
				     u32 sf, u32 th);

/**
 * csp_gmac_set_tx_queue_enable - set tx queue enable.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @mode: tx queue enable mode.
 */
void csp_gmac_set_tx_queue_enable(void *base_addr, u32 queue, u32 mode);

/**
 * csp_gmac_set_tx_queue_size - set tx queue size.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @size: tx queue size.
 */
void csp_gmac_set_tx_queue_size(void *base_addr, u32 queue, u32 size);

/**
 * csp_gmac_set_tx_queue_weight - set tx queue weight.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @weight: tx queue weight.
 */
void csp_gmac_set_tx_queue_weight(void *base_addr, u32 queue, u32 weight);

/**
 * csp_gmac_clr_qx_int_status - clear mtl queue[x] interrupt status.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @mask: interrupt bits to be clear.
 */
void csp_gmac_clr_qx_int_status(void *base_addr, u32 queue, u32 mask);

/**
 * csp_gmac_get_qx_int_status - get mtl queue[x] interrupt status.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 *
 * return queue[x] interrupt status.
 */
u32 csp_gmac_get_qx_int_status(void *base_addr, u32 queue);

/**
 * csp_gmac_set_rx_queue_threshold - set rx Store-and-Forward or set threshold.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @sf: 0, disable tx Store-and-Forward; !0, enable.
 * @th: rx threshold to set, if rx Store-and-Forward is disabled.
 */
void csp_gmac_set_rx_queue_threshold(void *base_addr, u32 queue,
				     u32 sf, u32 th);

/**
 * csp_gmac_set_rx_queue_size - set rx queue size.
 * @base_addr: base address of gmac controller.
 * @queue: queue number.
 * @size: rx queue size.
 */
void csp_gmac_set_rx_queue_size(void *base_addr, u32 queue, u32 size);

/**
 * csp_gmac_dma_soft_reset - dma software reset.
 * @base_addr: base address of gmac controller.
 */
void csp_gmac_dma_soft_reset(void *base_addr);

/**
 * csp_gmac_dma_soft_reset_status - get dma software reset status.
 * @base_addr: base address of gmac controller.
 *
 * return 0 if reset operation is completed; 1 if not completed.
 */
u32 csp_gmac_dma_soft_reset_status(void *base_addr);

/**
 * csp_gmac_set_axi_wr_osr_limit - set axi write outstanding request limit.
 * @base_addr: base address of gmac controller.
 * @limit: axi maximum write outstanding request limit.
 */
void csp_gmac_set_axi_wr_osr_limit(void *base_addr, u32 limit);

/**
 * csp_gmac_set_axi_rd_osr_limit - set axi read outstanding request limit.
 * @base_addr: base address of gmac controller.
 * @limit: axi maximum read outstanding request limit.
 */
void csp_gmac_set_axi_rd_osr_limit(void *base_addr, u32 limit);

/**
 * csp_gmac_set_addr_align_beat - enable or disable address-aligned beats.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_addr_align_beat(void *base_addr, u32 enable);

/**
 * csp_gmac_set_enhanced_address_mode - enable or disable enhanced address mode.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_enhanced_address_mode(void *base_addr, u32 enable);

/**
 * csp_gmac_set_axi_burst_len - set axi burst length.
 * @base_addr: base address of gmac controller.
 * @len: axi burst length.
 */
void csp_gmac_set_axi_burst_len(void *base_addr, u32 len);

/**
 * csp_gmac_set_en_address_mode - enable or disable fixed burst length.
 * @base_addr: base address of gmac controller.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_set_fixed_burst_len(void *base_addr, u32 enable);

/**
 * csp_gmac_set_dma_ch_8xpbl - enable or disable 8xpbl mode.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @enable: 0, disable; !0 enable.
 */
void csp_gmac_set_dma_ch_8xpbl(void *base_addr, u32 ch, u32 enable);

/**
 * csp_gmac_dma_ch_tx_enable - enable or disable dma channel tx.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_dma_ch_tx_enable(void *base_addr, u32 ch, u32 enable);

/**
 * csp_gmac_dma_ch_tso_enable - enable or disable tso.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_dma_ch_tso_enable(void *base_addr, u32 ch, u32 enable);

/**
 * csp_gmac_set_dma_ch_txpbl - set tx programmable burst length.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @txpbl: tx programmable burst length.
 */
void csp_gmac_set_dma_ch_txpbl(void *base_addr, u32 ch, u32 txpbl);

/**
 * csp_gmac_dma_ch_rx_enable - enable or disable dma channel rx.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @enable: 0, disable; !0, enable.
 */
void csp_gmac_dma_ch_rx_enable(void *base_addr, u32 ch, u32 enable);

/**
 * csp_gmac_set_dma_ch_rxpbl - set rx programmable burst length.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @rxpbl: rx programmable burst length.
 */
void csp_gmac_set_dma_ch_rxpbl(void *base_addr, u32 ch, u32 rxpbl);

/**
 * csp_gmac_set_dma_ch_rbsz - set rx buffer size.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @rbsz: rx buffer size.
 */
void csp_gmac_set_dma_ch_rbsz(void *base_addr, u32 ch, u32 rbsz);

/**
 * csp_gmac_set_tx_desc_base - set tx desc start address.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @addr: tx desc start address.
 */
void csp_gmac_set_tx_desc_base(void *base_addr, u32 ch, u32 addr);

/**
 * csp_gmac_set_rx_desc_base - set rx desc start address.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @addr: rx desc start address.
 */
void csp_gmac_set_rx_desc_base(void *base_addr, u32 ch, u32 addr);

/**
 * csp_gmac_set_tx_desc_tail - set tx desc tail pointer.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @tail: tx desc tail pointer.
 */
void csp_gmac_set_tx_desc_tail(void *base_addr, u32 ch, u32 tail);

/**
 * csp_gmac_set_rx_desc_tail - set rx desc tail pointer.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @tail: rx desc tail pointer.
 */
void csp_gmac_set_rx_desc_tail(void *base_addr, u32 ch, u32 tail);

/**
 * csp_gmac_set_tx_ring_len - set tx desc ring length.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @len: tx desc ring length.
 */
void csp_gmac_set_tx_ring_len(void *base_addr, u32 ch, u32 len);

/**
 * csp_gmac_set_rx_ring_len - set rx desc ring length.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @len: rx desc ring length.
 */
void csp_gmac_set_rx_ring_len(void *base_addr, u32 ch, u32 len);

/**
 * csp_gmac_dma_ch_int_enable - enable dma channel interrupt.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 */
void csp_gmac_dma_ch_int_enable(void *base_addr, u32 ch);

/**
 * csp_gmac_dma_ch_int_disable - disable dma channel interrupt.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 */
void csp_gmac_dma_ch_int_disable(void *base_addr, u32 ch);

/**
 * csp_gmac_set_dma_ch_rxwdt - set rx watchdog timer.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @rwt: rx interrupt watchdog timer count.
 */
void csp_gmac_set_dma_ch_rxwdt(void *base_addr, u32 ch, u32 rwt);

/**
 * csp_gmac_get_dma_ch_status - get dma channel status.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 *
 * return dma channel status.
 */
u32 csp_gmac_get_dma_ch_status(void *base_addr, u32 ch);

/**
 * csp_gmac_clr_dma_ch_status - clear dma channel status.
 * @base_addr: base address of gmac controller.
 * @ch: channel number.
 * @mask: dma channel status bits to be clear.
 */
void csp_gmac_clr_dma_ch_status(void *base_addr, u32 ch, u32 mask);

/**
 * csp_gmac_default_mac_addr - get default mac address.
 * @base_addr: base address of gmac controller.
 * @addr: buffer to receive the mac address.
 *
 * return 0 if success; otherwise failed.
 */
int csp_gmac_default_mac_addr(void *base_addr, u8 *addr);

#endif /* __GMAC_CSP_H__ */
